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OZ6912
Single-Slot ACPI CardBus Controller
FEATURES
* * * * * * * * * * * * * * * * * * *
ACPI-PCI Bus Power Management Interface Specification Rev 1.1 Compliant Supports OnNow LAN wakeup, OnNow Ring Indicate, PCI CLKRUN#, PME#, and CardBus CCLKRUN# Compliant with PCI specification v2.2, 2000 PC Card Standard 7.1 YentaTM PCI to PCMCIA CardBus Bridge register compatible ExCA (Exchangeable Card Architecture) compatible registers mappable in memory and I/O space TM Intel 82365SL PCIC Register Compatible Supports PCMCIA_ATA Specification Supports 5V/3.3V PC Cards and 3.3V CardBus cards Supports single PC Card or CardBus slot with hot insertion and removal Supports multiple FIFOs for PCI/CardBus data transfer Supports Direct Memory Access for PC/PCI and PCI/Way on PC Card socket Programmable interrupt protocol: PCI, PCI+ISA, PCI/Way, or PC/PCI interrupt signaling modes Win'98 IRQ and PC-98/99 compliant Supports parallel or serial interface for socket power control including devices from Micrel and TI Zoomed Video Support; Zoomed video buffer enable pins D3cold state PME# wakeup support 3.3Vaux Power Support Integrated PC 98/99 -Subsystem Vendor ID support, with auto lock bit LED Activity Pins
specification as defined by PCMCIA release 2.1. CardBus is intended to support "temporal" add-in functions on PC Cards, such as Memory cards, Network interfaces, FAX/Modems and other wireless communication cards, etc. The high performance and capability of the CardBus interface will enable the new development of many new functions and applications. The OZ6912 CardBus controller is compliant with the latest ACPI-PCI Bus Power Management Interface Specification. It supports all four power states and the PME# function for maximum power savings and ACPI compliance. Additional compliance to OnNow Power Management includes D3cold state support, paving the way for low sleep state power consumption and minimized resume times. To allow host software to reduce power consumption further, the OZ6912 provides a power-down mode in which internal clock distribution and the PC Card socket clocks are stopped. An advanced CMOS process is also used to minimize system power consumption. The OZ6912 single PCMCIA socket supports a mix and match 3.3V/5V 8/16-bit PC Card R2 card or 32-bit CardBus R3 card. The R2 card support is compatible with the Intel 82365SL PCIC controller, and the R3 card support is fully compliant with the 2000 PC Card Standard CardBus specification. The OZ6912 is a stand alone device, which means that it does not require an additional buffer chip for the PC Card socket interface. In addition, the OZ6912 supports dynamic PC Card hot insertion and removal, with auto configuration capabilities. The OZ6912 is fully compliant with the 33Mhz PCI Bus specification, v2.2. It supports a master device with internal CardBus direct data transfer. The OZ6912 implements a FIFO data buffer architecture between the PCI bus and CardBus socket interface to enhance data transfers to CardBus devices. The bi-directional FIFO buffer permits the OZ6912 to accept data from a target bus (PCI or CardBus interface) while simultaneously transferring data. This architecture not only speeds up data transfers but also prevents system deadlocks. The OZ6912 is a PCMCIA R2/CardBus controller, providing the most advanced design flexibility for PC Cards that interface with advanced notebook designs.
ORDERING INFORMATION
OZ6912T - 144pin LQFP OZ6912B - 144pin Mini-BGA
GENERAL DESCRIPTION
The OZ6912 is an ACPI and PC98/99 Logo Certified, high performance, single slot PC Card controller with a synchronous 32-bit bus master/target PCI interface. This PC Card to PCI bridge host controller is compliant with the 2000 PC Card Standard. This standard incorporates the new 32-bit CardBus while retaining the 16-bit PC Card
06/28/00 Copyright 2000 by O2Micro
OZ6912-SF-1.5 All Rights Reserved
Page 1 Patent Pending
OZ6912
Functional Block Diagram
PCI Interface
PCI Configuration/ PCI Function Control Registers Function Control Configuration/ Registers
PCI PCI Arbite Arbiter r
ACPI/ OnNow Power Management for PC99
Power Switch Power Control Contro Switch l
CardBu CardBus FIFO Data FIFO DatasBuffering Buffering
Interrupt Interrup Subsystem Subsyste t m
8/16-Bit 16PC PC Card Bit Machin Card Machine e
CardBus PC Card Machine and Arbiter
Powe Power Switc r Switch h Interface
Single PC Card Interface PC Card Interface
OZ6912-SF-1.5
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OZ6912
SYSTEM BLOCK DIAGRAM
The following diagram is a typical system block diagram utilizing the OZ6912 ACPI CardBus controller with other related chipsets.
CPU
VGA AGP North Bridge
Memory
PCI Bus
OZ6912 CardBus Controller
South Bridge
PC Card
ISA
OZ6912-SF-1.5
Page 3
OZ6912
PIN DIAGRAM - 144 Pin LQFP
A22/CTRDY# A15/CIRDY# A23/CFRAME# A12/CCBE2# A24/CAD17 GND A7/CAD18 A25/CAD18 VS2/CVS2 A6/CAD20 RESET/CRST# A5/CAD21 A4/CAD22 CORE_VCC INPACK#/CREQ# A3/CAD23 REG#/CCBE3# SOCKET_VCC A2/CAD24 A1/CAD25 A0/CAD26 GND VS1/CVS1 RDY/IREQ#/CINT# WAIT#/CSERR# BVD2/SPKR#/LED/CAUDIO BVD1/STSCHG#/RI#/CSTSCHG WP/IOIS16/CCLKRUN# CD2/CCD2# CORE_VCC D0/CAD27 D8/CAD28 D1/CAD29 D9/CAD30 D2/RFU D10/CAD31
111 1 444 2 432 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 3 3 3 789 11111111111111111111 1111111 111111 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0108 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 O2 Micro, Inc. 92 91 90 OZ6912 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 7 7 73 01 23 4 5 6 789 0 12 34 5 6 789 01 23 456 78 901 2 A16/CCLK A21/CDEVSEL# WE#/CGNT# A20/CSTOP# A14/CPERR# A19/CBLOCK# CORE_VCC A13/CPAR A18/RFU A8/CCBE1# A17/CAD16 A9/CAD14 IOW#/CAD15 A11/CAD12 GND IORD#/CAD13 OE#/CAD11 CE2#/CAD10 SOCKET_VCC A10/CAD9 CE1#/CCBE0# D15/CAD8 CORE_VCC D7/CAD7 D14/RFU D6/CAD5 D13/CAD6 D5/CAD3 D12/CAD4 D4/CAD1 GND D11/CAD2 D3/CAD0 CD1/CCD1# VCCD1#/SCLK VCCD0#/SDATA
REQ# GNT# AD31 AD30 AD29 GND AD28 AD27 AD26 AD25 AD24 C/BE3# IDSEL CORE_VCC AD23 AD22 AD21 PCI_VCC AD20 RST# PCI_CLK GND AD19 AD18 AD17 AD16 C/BE2# FRAME# IRDY# PCI_VCC TRDY# DEVSEL# STOP# PERR# SERR# PAR
VPPD1 VPPD0/SLATCH SUSPEND# MF6 MF5 MF4 GLOBAL_RST# MF3 MF2 AUX_VCC SPKR_OUT# MF1 MF0 RI_OUT/PME# GND AD0 AD1 AD2 AD3 AD4 AD5 AD6 PCI_VCC AD7 C/BE0# AD8 AD9 AD10 PCI_VCC AD11 GND AD12 AD13 AD14 AD15 C/BE1#
OZ6912-SF-1.5
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OZ6912
Pin List
Bold Text = Normal Default Pin Name
PCI Bus Interface Pins
Pin Name AD[31:0] Description PCI Bus Address/Data: These pins connect to PCI bus signals AD[31:0]. A Bus transaction consists of an address phase followed by one or more data phases. Pin Number LQFP BGA 3-5, 7-11, 15C2, C1, D4, D2, 17, 19, 23-26, D1, E4, E3, E2, 38-41, 43, 45F2, F1, G2, G3, 47, 49, 51-57 H3, H4, J1, J2, N2, M3, N3, K4, M4, K5, L5, M5, K6, M6, N6, M7, N7, L7, K7, N8 12, 27, 37, 48 E1, J3, N1, N5 Input TTL Type I/O Power Rail PCI_Vcc Drive PCI Spec
C/BE[3:0]#
FRAME#
IRDY#
TRDY#
STOP#
IDSEL
DEVSEL#
PERR#
SERR#
PCI Bus Command / Byte Enable: The command signaling and byte enables are multiplexed on the same pins. During the address phase of a transaction, C/BE[3:0]# are interpreted as the bus commands. During the data phase, C/BE[3:0]# are interpreted as byte enables. The byte enables are to be valid for the entirety of each data phase, and they indicate which bytes in the 32-bit data path are to carry meaningful data for the current data phase. Cycle Frame: This signal indicates to the OZ6912 that a bus transaction is beginning. While FRAME# is asserted, data transfers continue. When FRAME# is de-asserted, the transaction is in its final phase. Initiator Ready: This signal indicates the initiating agent's ability to complete the current data phase of the transaction. IRDY# is used in conjunction with TRDY#. Target Ready: This signal indicates target Agent's the OZ6912's ability to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. Stop: This signal indicates the current target is requesting the master to stop the current transaction. Initialization Device Select: This input is used as chip select during configuration read and write transactions. This is a point-to-point signal. IDSEL can be used as a chip select during configuration read and write transactions. Device Select: This signal is driven active LOW when the PCI address is recognized as supported, thereby acting as the target for the current PCI cycle. The Target must respond before timeout occurs or the cycle will terminate. Parity Error: The output is driven active LOW when a data parity error is detected during a write phase. System Error: This output is driven active LOW to indicate an address parity error.
TTL
I/O
PCI_Vcc
PCI Spec
28
J4
TTL
I/O
PCI_Vcc
PCI Spec
29
K1
TTL
I/O
PCI_Vcc
PCI Spec
31
K3
TTL
I/O
PCI_Vcc
PCI Spec
33
L2
TTL
I/O
PCI_Vcc
PCI Spec PCI Spec
13
F4
TTL
I
PCI_Vcc
32
L1
TTL
I/O
PCI_Vcc
PCI Spec
34
L3
-
TO
PCI_Vcc
PCI Spec PCI Spec
35
M1
-
TO
PCI_Vcc
OZ6912-SF-1.5
Page 5
OZ6912
Pin Name PAR Description Parity: This pin generates PCI parity and ensures even parity across AD[31:0] and C/BE[3:0]#. During the address phase, PAR is valid after one clock. With data phases, PAR is stable one clock after a write or read transaction. PCI Clock: This input provides timing for all transactions on the PCI bus to and from the OZ6912. All PCI bus signals, except RST#, are sampled and driven on the rising edge of PCI_CLK. This input can be operated at frequencies from 0 to 33 MHz. Device Reset: This input is used to initialize all registers and internal logic to their reset states and place most OZ6912 pins in a HIGHimpedance state. Grant: This signal indicates that access to the bus has been granted. Request: This signal indicates to the arbiter that the OZ6912 requests use of the bus. Pin Number LQFP 36 BGA M2 Input TTL Type I/O Power Rail PCI_Vcc Drive PCI Spec
PCI_CLK
21
H1
-
I
PCI_Vcc
-
RST#
20
G4
-
I
AUX_Vcc
-
GNT# REQ#
2 1
B1 A1
TTL -
I TO
PCI_Vcc PCI_Vcc
PCI Spec PCI Spec
Power Control and General Interface Pins
Pin Name RI_OUT/ PME# Description Ring Indicate Out: This pin is Ring Indicate when the following occurs while O2 Mode Control B Register (index 2Eh) bit 7 is set to 1: 1) Power Control (Index+02h) bit 7 set to 1 2) Interrupt and General Control (Index+03h) bit 7 set to 1 3) PCI O2Micro Control 2 (Offset: D4h) bit X = 0 Power Management Event: A power management event is the process by which the OZ6912 can request a change of its power consumption state. Usually, a PME occurs during a request to change from a power saving state to the fully operational state. Speaker Output: This output can be used to support PC Card audio output. See O2 Mode E Register (Index + 3Eh), bit 1. Multifunction Terminal [6:0]: See PCI Multifunction MUX Register (Offset:08h). Suspend: This signal is used to protect the internal registers from clearing when the PCI RST# signal is asserted. When low, this signal is used to mask the PCI RESET during suspend. This pin can be used during suspend to prevent controller reset. Global_Reset#: This signal can be connected to either PCI reset or ACPI reset depending on system implementation. If the D3 cold state is implemented, this signal should be connected to the ACPI reset, otherwise, connect to PCI reset. This signal can reset the PME content under the D3 cold state if AUX_VCC is provided. Pin Number LQFP BGA 59 L8 Input Type TO Power Rail Aux_Vcc Drive 4mA
SPKR_OUT#
62
M9
TTL
I/O
Aux_Vcc
6mA
MF[6:0]
60-61, 64-65, 67-69 70
SUSPEND#
K8, N9, K9, N10, L10, N11, M11 L11
TTL
I/O
Aux_Vcc
6mA
TTL
I
Aux_Vcc
-
G_RST#
66
M10
TTL
I
Aux_Vcc
-
OZ6912-SF-1.5
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OZ6912
Pin Name VPPD0/ SLATCH Description VPPD0: This power input is used with parallel power control chip SLATCH: This output controls a serial interface power control chip. VPPD1: This power input is used a parallel power interface chip. VCCD0#: Rail power inputs for use with a parallel power control chip. Serial Data: This pin serves as output DATA pin when used with a serial interface of serial power control chip. VCCD1#: Rail power inputs for use with a parallel power control chip. Serial Clock: The input is used as a reference clock (10-100kHz, usually 32kHz) to control a serial power control chips. By setting PCI O2Micro Control 2 register (Offset: D4h) bit 13 to 1, SCLK is an output. Default is input mode. Pin Number LQFP BGA 71 N12 Input TTL Type I/O Power Rail Aux_Vcc Drive 6mA
VPPD1 VCCD0#/ SDATA
72 73
M12 N13
TTL
TO I/O
Aux_Vcc Aux_Vcc
6mA 6mA
VCCD1#/ SCLK
74
M13
TTL
I/O
Aux_Vcc
6mA
OZ6912-SF-1.5
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OZ6912
PC Card Socket Interface Pins
Refer to PCI Bus Interface pin descriptions for details on CardBus function. EXCEPTIONS: CCD[2:1]#, CAUDIO, CSTSCHG, CVS[2:1]
Pin Name REG#/ CCBE3# Description Register Access: During PC Card memory cycles, this output chooses between Attribute and Common Memory. During I/O cycles for non-DMA transfers, this signal is active (low). During ATA mode, this signal is always inactive. For DMA cycles on the OZ6912 to a DMA-capable card, REG# becomes DACK to the PCMCIA card. CardBus Command Byte Enable: In CardBus mode, this pin is the CCBE3#. Address: PC Card socket address 25:24 outputs. CardBus Address/Data: CardBus mode, these pins are the CAD bits 19 and 17. Address: PC Card socket address 23 output. CardBus Frame: In CardBus mode, this pin is the CFRAME# signal. Address: PC Card socket address 22 output. CardBus Target Ready: In CardBus mode, this pin is the CTRDY# signal. Address: PC Card socket address 21 output. CardBus Device Select: In CardBus mode, this pin is the CDEVSEL# signal. Address: PC Card socket address 20 output. CardBus Stop: In CardBus mode, this pin is the CSTOP# signal. Address: PC Card socket address 19 output. CardBus Lock: In CardBus mode, this signal is the CBLOCK# signal used for locked transactions. Address: PC Card socket address 18 output. Reserved: In CardBus mode, this pin is reserved for future use. Address: PC Card socket address 17 output. CardBus Address/Data: In CardBus mode, this pin is the CAD bit 16. Address: PC Card socket address 16 output. CardBus Clock: In CardBus mode, this pin supplies the clock to the inserted card. Pin Number LQFP BGA 125 B7 Input TTL Type I/O Power Rail Socket _Vcc Drive CardBus spec.
A[25:24]/ CAD[19, 17] A23/ CFRAME# A22/ CTRDY# A21/ CDEVSEL# A20/ CSTOP# A19/ CBLOCK# A18/ RFU A17/ CAD16 A16/ CCLK#
116, 113
A10, D10
TTL
I/O
Socket _Vcc Socket _Vcc Socket _Vcc Socket _Vcc Socket _Vcc Socket _Vcc Socket _Vcc Socket _Vcc Socket _Vcc
CardBus spec. CardBus spec. CardBus spec. CardBus spec. CardBus spec. CardBus spec. CardBus spec. CardBus spec. CardBus spec.
111
B11
TTL
I/O
109
A13
TTL
I/OPU I/OPU I/OPU I/OPU TO
107
B13
TTL
105
C12
TTL
103
D11
TTL
100
E10
TTL
98
E12
TTL
I/O
108
B12
TTL
I/O
OZ6912-SF-1.5
Page 8
OZ6912
Pin Name A15/ CIRDY# Description Address: PC Card socket address 15 output. CardBus Initiator Ready: In CardBus mode, this pin is the CIRDY# signal. Address: PC Card socket address 14 output. CardBus Parity Error: CardBus mode, this pin is the CPERR# signal. Address: PC Card socket address 13 output. CardBus Parity: In CardBus mode, this pin is the CPAR signal. Address: PC Card socket address 12 output. CardBus Command/Byte Enable: In CardBus mode, this pin is the CCBE2# signal. Address: PC Card socket address 11:9 output. CardBus Address/Data: In CardBus mode, these pins are the CAD bits 12, 9 and 14. Address: PC Card socket address 8 output. CardBus Command/Byte Enable: In CardBus mode, this pin is the CCBE1# signal. Address: PC Card socket address 7:0 outputs. CardBus Address/Data: In CardBus mode, these pins are the CAD bits 18 and 20:26. Data: PC Card socket I/O data bit 15. CardBus Address/Data: In CardBus mode, this pin is the CAD bit 8. Data: PC Card socket I/O data bit 14. Reserved: In CardBus mode, this pin is reserved for future use. Data: PC Card socket I/O data bits 13:3. CardBus Address/Data: In CardBus mode, this pin is the CAD bit 6 4, 2, 31, 30, 28, 7, 5, 3, 1, and 0, respectively. Data: PC Card socket I/O data bit 2. Reserved: In CardBus mode, this pin is reserved for future use. Data: PC Card socket I/O data bits 1:0. CardBus Address/Data: In CardBus mode, these pins are the CAD bits 29 and 27, respectively. Output Enable: This output goes active (low) to indicate a memory read from the OZ6912 to PC Card. CardBus Address/Data: In CardBus mode, this pin is the CAD bit 11. Write Enable: This output goes active (low) to indicate a memory write from the OZ6912 to the PC Card socket. CardBus Grant: In CardBus mode, this pin is the CGNT# signal. Pin Number LQFP BGA 110 A12 Input TTL Type I/OPU Power Rail Socket _Vcc Drive CardBus spec.
A14/ CPERR#
104
C13
TTL
I/OPU
Socket _Vcc
CardBus spec.
A13/ CPAR
101
D13
TTL
I/O
Socket _Vcc
CardBus spec.
A12/ CCBE2#
112
A11
TTL
I/O
Socket _Vcc
CardBus spec.
A[11:9]/ CAD [12,9,14] A8/ CCBE1#
95, 89, 97
F11, G12, E13
TTL
I/O
Socket _Vcc
CardBus spec.
99
E11
TTL
I/O
Socket _Vcc
CardBus spec.
A[7:0]/ CAD[18] [20:26] D15/ CAD8
115, 118, 120, 121, 124, 127, 128, 129 87
B10, C9, A9, D8, A8, C7, D7, A6 H12
TTL
I/O
Socket _Vcc
CardBus spec.
TTL
I/O
Socket _Vcc
CardBus spec.
D14/ RFU
84
J13
TTL
I/O
Socket _Vcc
CardBus spec.
D[13:3]/ CAD[6, 4, 2, 31, 30, 28, 7, 5, 3, 1, 0]
82, 80, 77, 144, 142, 140, 85, 83, 81, 79, 76
D2/ RFU
143
J11, K13, K10, B2, C3, A3, H10, J12, J10, K12, L13 A2
TTL
I/O
Socket _Vcc
CardBus spec.
TTL
I/O
Socket _Vcc
CardBus spec.
D[1:0]/ CAD[29,27]
141, 139
B3, C4
TTL
I/O
Socket _Vcc
CardBus spec.
OE#/ CAD11
92
G10
TTL
I/O
Socket _Vcc
CardBus spec.
WE#/ CGNT#
106
C11
TTL
TO
Socket _Vcc
CardBus spec.
OZ6912-SF-1.5
Page 9
OZ6912
Pin Name IORD#/ CAD13 Description I/O Read: This output goes active (low) for I/O reads from the OZ6912 to the socket. CardBus Address/Data: In CardBus mode, this pin is the CAD bit 13. I/O Write: This output goes active (low) for I/O writes from the OZ6912 to the socket. CardBus Address/Data: In CardBus mode, this pin is the CAD bit 15. Write Protect / I/O is 16-Bit: In Memory mode, this input is indicates the status of the write protect switch on the PC Card. In I/O mode, this input indicates the size of current data transfer on the PC Card. CardBus Clock Run: In CardBus mode, this pin is the CCLKRUN# signal, which starts and stops the CardBus CCLK. To enable the CLKRUN# signal, ExCA register 3Bh bit[3:2] must be enabled. Input Acknowledge: The INPACK# function is not applicable in PCI bus environments. This pin is provided for Legacy card compatibility. CardBus Request: In CardBus mode, this pin is the CREQ# signal. Ready / Interrupt Request: In Memory mode, this input indicates that the card is ready or busy. In I/O mode, this input indicates a card interrupt request. CardBus Interrupt: In CardBus mode, this pin is the CINT# signal. This signal is active-low and level-sensitive. Wait: This pin is driven by the PC Card to delay completion of the current cycle. CardBus System Error: In CardBus mode, this pin is the CSERR# signal. Card Detect: These inputs indicate a card is present in the socket. They are internally pulled high to AUX_VCC. CardBus Card Detect: In CardBus mode, these inputs are used with CVS[2:1] to detect presence and type of card. Card Enable 2: This pin is driven low to control byte/word card access. CE2# enables oddnumbered address bytes. CardBus Address/Data: In CardBus mode, this pin is the CAD bit 10. Card Enable 1: This pin is driven low to control byte/word card access. CE1# enables evennumbered address bytes. When configured for 8bit cards, CE1# is active and A0 is used to indicate access of odd- or even-numbered bytes. CardBus Command/Byte Enable: In CardBus mode, this pin is the CCBEO# signal. Pin Number LQFP BGA 93 F13 Input TTL Type I/O Power Rail Socket _Vcc Drive CardBus spec.
IOW#/ CAD15
96
F10
TTL
I/O
Socket _Vcc
CardBus spec.
WP/ IOIS16#/ CCLKRUN#
136
D5
TTL
I/O-PU
Socket _Vcc
CardBus spec.
INPACK#/ CREQ#
123
B8
-
I-PU
Socket _Vcc
CardBus spec.
RDY/IREQ#/ CINT#
132
D6
-
I-PU
Socket _Vcc
CardBus spec.
WAIT#/ CSERR#
133
A5
TTL
I-PU
Socket _Vcc
CardBus spec.
CD[2:1]/ CCD[2:1]#
137, 75
A4, L12
TTL
I-PUSchmitt
Aux_Vcc
CardBus spec.
CE2#/ CAD10
91
G11
TTL
I/O
Socket _Vcc
CardBus spec.
CE1#/ CCBE0#
88
H13
TTL
I/O
Socket _Vcc
CardBus spec.
OZ6912-SF-1.5
Page 10
OZ6912
Pin Name RESET/ CRST# Description Reset: This active high output resets the card. To prevent reset glitches, this signal is highimpedance unless a card is seated in the socket, card power is applied, and the card's interface signals are enabled. CardBus Reset: In CardBus mode, this pin is the CRST# output. Battery Voltage Detect 2 / Speaker / LED: In Memory mode, this input serves as the BVD2 (battery warning status) input. In I/O mode, this input can be configured as the card's SPKR# audio input or drive-active LED input. CardBus Audio: In CardBus mode, this pin is the CAUDIO input. Battery Voltage Detect 1 / Status Change / Ring Indicate: In Memory mode, this is the BVD1 (battery-dead status) input. In I/O mode, this is the STSCHG# input indicating that the card's internal status has changed, or the ring indicates input for wakeup-on-ring system power management support. See bit 7 of the Interrupt and General Control register (03h). CardBus Status Change: In CardBus mode, this pin is the CSTSCHG. This pin can be used to generate PME#. Voltage Sense: These pins are used in conjunction with CD[2:1] to determine the type and voltage of a card. These pins are internally pulled high to AUX_VCC. See Table 1. CardBus Voltage Sense: In CardBus mode, these pins are the CVS[2:1] pins. Socket Power: These pins are the power rail input for the socket interface control logic. These pins can be 0, 3.3, or 5 V,. The socket interface outputs will operate at the voltage applied to these pins. Pin Number LQFP BGA 119 B9 Input TTL Type TO Power Rail Socket _Vcc Drive CardBus spec.
BVD2/SPKR#/ LED/CAUDIO
134
B5
-
I-PU
Socket _Vcc
-
BVD1/ STSCHG#/RI# /CSTSCHG
135
C5
-
I-PU
Socket _Vcc
-
VS[2:1]/ CVS[2:1]
117, 131
D9, C6
TTL
I/O-PU
Aux_Vcc
CardBus spec.
SOCKET_VCC
90, 126
G13, A7
-
PWR
-
-
OZ6912-SF-1.5
Page 11
OZ6912
Power, Ground, and Reserved Pins
Pin Name AUX_VCC Description Auxiliary VCC: This pin is connected to the system's 3.3/5V power supply. For the device to 5V tolerant, connect to +5V power. CORE_VCC: This pin provides power to the core circuitry of the OZ6912. It must be connected to a 3.3V power supply. PCI Bus VCC: These pins can be connected to either a 3.3V or5V power supply. The PCI bus interface will operate at the voltage applied to these pins, independent of the voltage applied to other OZ6912 pin groups. System Ground Pin Number LQFP BGA 63 L9 Input Type PWR Power Rail Drive -
CORE_VCC
14, 86, 102, 122, 138 18, 30, 44, 50
PCI_VCC
F3, H11, D12, C8 B4 G1, K2, N4, L6
-
PWR
-
-
-
PWR
-
-
GND
6, 22, 42, 58, 78, 94, 114, 130
D3, H2, L4, M8, K11, F12, C10, B6
-
GND
-
-
Legend
I/O Type I I-PU I-PU Schmitt O OD TO TO-PU OD-PU PWR Description Input Pin Input pin with internal pull-up Input pin with internal pull-up and Schmitt trigger Output Open-drain Tri-state output Tri-state output with internal pull-up Open-drain output with internal pull-up Power pin Power Rail 1 2 3 4 Source of Output's Power AUX_VCC: outputs powered from AUX_VCC SOCKET_VCC: outputs powered from the socket PCI_VCC: outputs powered from PCI bus power supply CORE_VCC: outputs powered from the CORE_VCC
OZ6912-SF-1.5
Page 12
OZ6912
Package Information - 144 Pin LQFP
He E A2 A1 Y
Hd D
L
0.08(0.003)
M
1
c
MILLIMETER SYMBOL
MIN. NOM. MAX. MIN. NOM. MAX.
e
b
INCH
A1 A2
GAGE PLANE
0.05
0.10
0.15
0.002
0.004
0.006
1.35
1.40
1.45
0.053
0.055
0.057
b
0.25
0.17
0.22
0.27
0.007
0.009
0.011
c D L E e Hd He L L1 Y
0.090
0.200
0.004
0.008
20.00
0.787
20.00
0.787
0.50
0.020
22.00
0.866
22.00
0.866
0.45
0.60
0.75
0.018
0.024
0.030
1.00
0.039
0.08
0.003
0
7
0
7
OZ6912-SF-1.5
Page 13
OZ6912
144 Pin Mini - BGA
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. "e" REPRESENTS THE SOLDER BALL GRID PITCH. 3. "N" REPRESENTS THE MAXIMUM NUMBER OF SOLDER BALLS FOR MATRIX SIZE M1 AND M2. 4. DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER AFTER REFLOW AND PARALLEL TO PRIMARY DATUM Z, THE ORIGINAL SOLDER BALL DIAMETER IS 0.45 mm. 5. PRIMARY DATUM Z AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 6. A1 CORNER MUST BE IDENTIFIED BY INK MARK, METALLIZED MARKINGS, IDENTATION OR OTHER FEATURE OF PACKAGE BODY, LID OR INTEGRAL HEATSLUG, ON THE TOP SURFACE OF THE PACKAGE. 7. SOLDER BALL DEPOPULATION IS ALLOWED. DEPOPULATION IS THE OMISSION OF BALLS FROM A FULL MATRIX (M1 OR M2). 8. BALL PAD A1 CORNER INDICATOR (NC) SOLDER BALL
OZ6912-SF-1.5
Page 14

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